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71M6545/71M6545H Data Sheet
Name
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
Location
2457[6]
2457[7]
2458[7]
2458[6]
SFR 9E
Rst
0
0
0
0
0
Wk
–
–
–
–
0
Dir
R/W
R/W
R/W
R/W
R/W
Description
Causes VPULSE to be output on DIO1.
Causes WPULSE to be output on DIO0.
Causes XPULSE to be output on DIO6.
Causes YPULSE to be output on DIO7.
Serial EEPROM interface data.
Serial EEPROM interface control.
EECTRL[7:0]
SFR 9F
0
0
R/W
Status
Bit
7
Name
ERROR
Read/
Write
R
Reset
State
0
Polarity Description
Positive 1 when an illegal command is received.
6
BUSY
R
0
Positive 1 when serial data bus is busy.
5
RX_ACK
R
1
Positive
1 indicates that the EEPROM sent an
ACK bit.
Specifies th e power equation.
Description
Element 0
EQU[2:0]
3
2 element, 4W,
3 φ Delta
4
2 element, 4W,
3 φ Wye
5*
3 element, 4W,
3 φ Wye
EQU[2:0]
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
2106[7:5]
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
0
0
0
0
R/W
R/W
Element Element Recommended
1 2 MUX Sequence
VA(IA -IB)/2 0 VC IC IA VA IB IC VC
VA(IA-IB)/2 VB(IC-IB)/2 0 IA VA IB VB IC
VA IA VB IB VC IC IA VA IB VB IC VC
Note:
*The available CE codes implements only equation 5. Contact your local Maxim representative to obtain
CE code for equations 3 and 4.
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, etc. The
bits are set by hardware and cannot be set by writing a 1. The bits are reset by writing
0. Note that if one of these interrupts is to enabled, its corresponding 8051 EX enable
bit must also be set. See 2.4.10 Interrupts , for details.
90
v2
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